The mode of loopy behavior in the silicon mesa transistors is similar to germanium. Mesa transistors had the collector diffused into the silicon over the entire wafer. The emitter was produced by a second diffusion or an alloy process (micro-epitaxy) and the emitter and base connections were covered with wax (or later photoresist) and were protected from an etch which went through the collector junction leaving the emitter and base on a tiny mesa of silicon. These junctions had no oxide protection except for the extremely thin native oxide and were sensitive to surface contamination as were the germanium emitter and collector junctions. The cans that transistors were put in or the plastic encapsulation of low cost transistors were to provide a hermetic seal and protect the sensitive collector junction. Contamination inside the can or any leaks resulted in leaky transistors.

The experimental tools we had were primitive compared to those even a few years later when we came first to really understand silicon junction passivation by oxides and through that to have some affirmation of what was deduced from primitive experiments for unprotected silicon and germanium junctions. There were some very early lessons from the solid logic technology (SLT) planar transistors used for the IBM 360. The theory of that design was that the transistors were protected by a low temperature powdered glass layer put onto the surface and then melted to give a hermetic seal to the junctions. This in theory would stabilize the transistors, but the theory didn't work because sodium atoms in the SiO2 layer lying under the frit glass layer were mobile ... unless the transistors had that locked up in a phosphosilicate glass layer from the emitter on NPN transistors. PNP transistors didn't have problems with surface inversion and were stable without the psg layer. That really didn't come out in technical publications until the advent of field effect transistors where the role of sodium in the SiO2 layer was a major issue in controlling both leakage and threshold voltage. IBM used PSG, while Intel and others essentially eliminated sodium by lots of washing before any thermal cycle which could lock fingerprints or other sodium contamination oxides.

(a) In the presence of bare copper in an oxygen free ambient, power aging degrades the emitter parameters and gain. Only partial recovery can be achieved by etching into the bulk silicon or by heating the device at 300�C (bulk failure). (b) In gold plated and/or oxygen backfilled cans, soft, loopy reverse junction characteristics develop under both temperature and power agings, first on the collector and later on the emitter. Both junctions. recover completely upon opening the can and drying the transistor surface (surface failure). Surface failure is caused by water adsorption over the surface of the silicon wafer. Experimental evidence, including aging experiments in atomic hydrogen, is presented to demonstrate that the bulk failure is caused by copper contamination in the bulk silicon. Copper is transferred from the can to the wafer via a volatile hydride. It diffuses into the silicon and becomes electrically active during power aging. Qualitative explanations are offered for both failure modes. Surface failure is due to surface states introduced by the adsorbed water and/or ionic conduction. In order to explain bulk failure, the solubility and precipitation of copper is examined over the transistor profile and the effect of field on the migration of copper in silicon is taken into account.

Just Plain Alloy Transistors – IBM Style

The 1401 came before we were doing diffusion of impurities into semiconductors. That came a little later. These were made on wafers aligned crystalographically with the surface being a <111> face. This is the slow dissolving face with many etches and also with the metals used for the emitter and collector alloy. The alloying is a crystalographic micro-etching by the metal "dots" used for emitter and collector. This gave a near-crystalographic flat bottom to the extent of the melting. The initial steps of the cooling were a recrystalization heavily doped with the appropriate impurity (gallium for pnp and probably antimony for npn). As the cooling proceeded rapidly, the melt became a mix of metal and polycrystaline germanium, getting more metallic toward the surface.

This alloying was a low temperature process done in a reducing atmosphere to help get wetting. The "clean-up" etches used afterwards were to both etch the metal back a little because it may have spread out over the base surface where there had been no alloying and also to get the surface back to an appropriate condition so that the transistor leakage at the surface was low.

The wafers were diamond cut from an oriented crystal, then mechanically polished and etched with an anisotropic etch to remove about a micron or so of lapping damage. It was fairly deep in germanium which is mechanically weaker than silicon. In the late 1960's we would have used a chemical-mechanical polish instead which was (if I remember right) a sodium hypochorite solution and a non-woven fabric pad, without any abrasive.

My frail memory cannot remember the etchants used and I haven't uncovered my PhD thesis which probably had some of the formulations in it. It hasn't been unpacked since it got moved to California a decade ago.

These wafers were then ultrasonically cut up to make round chips of controlled thickness. The polishing was probably developed by Earle Harden, a toolmaker with very skilled fingers for creating small transistors and a love for precision machining through lapping.. I first worked with him as one of my teachers and then was his manager for some years where I utilized his skills in many ways.

After he left me, he joined David Thmpson on the project that made the first thin first thin film magnetic recording heads. Earle pretty uch defined the diamond lapping process for the air bearing surface that isstill used today. I had a small role in that project. David,Luby Romankiw and I kicked over the idea of using lithography and thin films for recording heads. I had the ability to quickly make masks using the fly's eye lens which gave me a 2 micron or so capability on-axis degrading from spherical aberration. Knowing the limits and with a decision on the number of turns, I designed the masks and cut them in rubylith at 500x, so I might claim to be the designer. I made the masks after hours since it wasn't part of my day job.

The wafers were relatively lightly doped in order to get the high ration of carrier concentration between emitter and base. This was of course a compromise between current gain and base resistance. It was also the reason for the ring washer base contact. In essence, these transistors were different from any silicon bipolar transistors which always had fairly high surface concentrations surrounding the emitter which naturally came from the double diffused emitter/base and helped suppress the emission at the edges of the emitter. It also made the surface of the junction less sensitive to surface inversion.

So we have a lightly doped base region. I don't know what etchants were used, but the final etch and blow dry would be intended to leave the surface in a low leakage state at both emitter and collector. The reason for the glass metal lead header and soldered cap was to hermetically seal the transistor in an environment where it wouldn't be subject to changing moisture and other contaminants. It worked remarkably well for many years.

I believe that all the "loopy" transistors we are looking at are ones which have surface contamination. While Pat Mooney is a good reference for deep level traps in semiconductors, including germanium, I don't think that is the big issue here. As I recall, Pat came to IBM and worked toward the end of the mid 1960's germanium program looking at deep traps, although we never got to long term passivation for that because silicon was close enough to Ge in speed at that time, that you wouldn't go backward for the 1.e to 2 times we eventually understood as its superiority, at least at that time. Its time may come, though.

The etchant would presumable leave the surface in some sort of condition that we didn't come to properly appreciate until we made surface devices in silicon. There, with silicon oxide structures (MOS) we learned about flat band voltages and about charge creating electric fields at or above the surface. That all came in in the early 1970's.

I got to go back to my roots in semiconductor capacitance again with MOS as I had with junction capacitance. None of the MOS work was published because my real focus was on automated measurements and lithography, but it gave Thomas Garwin, a summer student, a great experience while he was deciding whether to do physics or history. He went to Harvard and did history (of science).

I believe that Hwa Yu at IBM did some work on germanium FET devices after the bipolar program. I really didn't ever talk to him much about that because his boss thought I was a traitor to kill the bipolar program I'd started when we discovered a flaw in the underlying assumptions of superiority to silicon. The problem was the limiting velocity of electrons in germanium (similar but not as abrupt as what causes Gunn Effect in GaAs).

Let me assume that the surfaces were near flat band. They would be relatively easy to move away from that if there was ionic charge at or near the surface. The light doping would make it relatively easy to either get an accumulated surface or the alternate of a depleted or inverted surface.

Since we had both npn and pnp transistors, I would expect changes due to the environment to be different for the two types of transistors, so we need to look for differences between the two and see if we can explain both phenomenon.

Let's look at the parameters. There are voltage breakdown and thermal effects on leakage. There are effects from either surface charge depletion or inversion layers. I believe that there were some papers on inversion layers and transistor turn-off, but I don't remember the terms we might have used to described them before we understood MOS.

OK .. a thought!!! You might be able to get some MOS measurements if you could take a small anodized aluminum or titanium film spot as one electrode and place it on the base surface and do a MOS capacitance measurement. It would need a soft backing to get good contact without changing the surface much. Might be too invasive.

We need to think through the effect of an accumulated, depleted, or inverted surface on transistor behavior. That includes the emitter being expanded by an inversion layer which would become more conductive and inject carriers during forward bias of the EB junction. When the transistor is turned off, the inversion layer might be partly or fully cut off from the inversion leaving the inversion still emitting. This would also be a region of the transistor where the carriers take longer to get to the collector. I believe this explanation is in the literature, but don't know where to find it. It may only have been an oral paper and never published on paper.

On the other side you need to look at what a strongly inverted surface would so and whether it would affect breakdown, Particularly you might need to understand this as perhaps having a thermal sensitivity.

Finally, you need to look at the effect of saturation in the transistor. This is another circuit effect that is essentially loopy. It takes a while for the transistor to shut off. I believe that all the 1401 circuits are saturating and that there is emission into the bulk regions of the base that take time to clean out either by lifetime or carriers getting to the collector as its voltage rises.

Lots of this stuff changed a lot when we went to diffusion and epitaxial base layers with a base diffusion to lower base resistance, much less space between emitter and base contacts. And diffused emitters. At that point the impurity concentrations at the semiconductor surface were much higher.

We can learn about that era when we decide to restore one of the few Stretch or 7090 machines. Those transistors were very much like the 1401, but they had a diffused base (speeding carriers across because of its impurity gradient) and much higher impurity concentration of the base surface, even though they were structurally very similar to the 1401 transistors.

The post-alloy diffused transistors we and TI worked on in the mid 1960's were real planar structure transistors and had dimensions from lithography in the 2.5 micron range. TI was interested in low noise from low base resistance and we were interested in maximum switching speed.

We gathered about 11:30, and it soon became evident that hand waving was not doing it - enter the white board - the engineer's mouth piece. left to right, Bill Newman (who had provided much of the photographic evidence), Rick Dill, Constantin Bulucea

About 12:30, the rest of the resortation/maintence crew came to eat their lunches. Note the photos of the evidence on the projection screen. Here Robert Garner is ... I didn't understand ;-)) The technical discussions continued until about 1:30 when business pressures called some away.

It was evident that more evidence and more test conditions were needed. At the next gathering Robert will bring his specialized 'scope, more transistors, and a test setup with more options.

This picture, of Professor Rick in full voice, was taken by Constantin. Note that the diagrams have shakey "doping" boundaries, and there are no equations to threaten and intimidate "the rest of us" ;-))

In preparation for the April, 6th meeting, Robert prepared 12 photographs of I/V curves. This one is as confusing as any. Hint - there are not supposed to be any loops present, just curves.

The group gathered in the CHM 1401 Workshop at 11:00 to watch Robert Garner demo some loopy transistors on his transistor curve tracer (a plug_in to a Tektronix scope).
There were many interesting (and confusing) displays, including some that looked like a pine tree cut length wise and a stalk of Brussel sprouts cut length wise. [I hope Constantin got some pictures.]

The meeting reconvened in a conference room with a projector and screen.
Constantin Bulucea gave a PowerPoint presentation which helped guide the very animated discussions.
Slide # 1, 2, 3, 4, 5, 6, 7, 8, 9
or as a .pdf

I confirm receiving all the articles. Kingston appears to be the most articulated and intriguing on surface channels (oxygen helps reducing them, nitrogen aggravates!). Thanks for all.

To continue our device physics thinking, it is important to know more information on the voltage ramps applied by your curve tracer: what shape, what speed? I say this is important because the next step should be the analysis of the dynamics of some competing phenomena:

1. Charge moving due to changes in electric field (here the speed of your ramp is important);

2. Carrier generation in surface depletion layers (here temperature comes into picture);

3. Carrier recombination in the base region (here device geometry makes simple calculations virtually impossible).

The most practical thing we can do is to repare some transistors for the sake of proving, beyond any doubt, that ambient contamination degraded them. We obviously need Rick Dill's recollections or records on the chemistry involved in manufacturing. The rest remains nice, possibly correct, speculation.

Constantin

PS - For those who are still not convinced on surface depletion (or space-charge) layers, here is a definitive, most pragmatic proof from Andy Grove's book. When I browsed this book in a bookstore, long time before the Internet and Amazon.com, and saw the picture below, I decided to buy it instantly!

The concepts of surface accumulation, depletion, and inversion are all there, but not related to specific charges such as sodium in the oxide or gate electrodes on the oxide or buried within it. In the late 1950's there was work on surface physics at IBM, but I forget the name of the guy doing the work. He was also involved in understanding what happened when our phospho-silicate glass was etched off the top layer of our SLT transistor oxides. This layer captured the mobile sodium ions and kept them well away from the surface and less important in driving surface interface fields.

OK, I finally uncovered my PhD thesis. It's fun to look back at it. It is very clear that I didn't know what was happening at the surface of germanium on unijunction transistors. As you know, I wasn't alone in that. It was also fun to see what I'd done with a computer and simulation with essentially no help and guidance. The IBM 650 was, to me looking back, my first personal computer. Using it to track fields and carriers in a germaniuim device was fun and I knew of no one else doing it. Unfortunately we only published our work (meeting the department demand for publication) was very obscure conference, SWIRECO in Austin, TX. SWIRECO was the Southwest IRE conference. Yes it was before IEEE.

The good news is that I have some suggestions about how to repair some of the leaky transistors if they aren't too far gone. It should be reasonably safe.

The most talked about etch in the early days of BTL work was CP4, a generic etchant with various formulations, but usually a mix of HF, HNO3, and Acetic acid with bromine in some formulations. In my observation, it gave surfaces with high surface recombination. The terms of surface accumulation, depletion, and inversion were not used in the 1957 era.

Two etch formulations I used that gave good surfaces on n-type germanium were:
     10% H2O2 solution dip
     15% NaOH solution electrolytic etc

Neither of these remove significant amounts of the germanium crystal, but they do seem to "clean" the surface so that the surfaces improve the measured lifetime within the device.

I would suggest starting with the H2O2 dip.
We will need de-ionized water if it is easy to find for pre-wash and post-wash.
We will also need it to dilute the H2O2 from a more concentrated level, unless a source at 10% is easy to find.
We would like low pressure dry nitrogen for blow-off, but if that is unavailable, air is a possible substitute.

This isn't heavy chemistry so we won't need a chem hood, but a blotter mat on any work bench might be a good idea.

Another document that might be useful, but I haven't found it, is a thick report we put together when we terminated our mid 1960's attempts to make germanium transistors that would switch faster than silicon ones. That had things like the chemical-mechanical polishing with sodium hypochorite solution and no abrasives to etch the surfaces to below the damage depth from mechanical polishing. That got us flat undamaged surfaces on the dislocation free crystals we were able to grow at that time.

Enough for tonight.

I'm making a copy of the thesis

Rick

One is hydrogen peroxide.

The other is sodium hydroxde.

We will need quality water (deionized preferable), although tap water may be adequate. That is all I had for my early germanium unijunction transistor building days.

CP-4 is out of the question, although it was famous (infamous) in early transistors such as point contact material preparation. My experience with it was that it led to high surface leakage (surface recombination), although that is not a scientific conclusion.

Both of my "etchants" essentially deal with the surface and do not rapidly attack the semiconductor. We can try them sequentially with testing after each. Neither has dangerous vapors, so a chem hood is not particularly required. Skin or hair contact with peroxide causes whitening, but no significant damage. Sodium hydroxide does turn the skin into "soap", but gloves are adequate protection. I suggest no imbibing of either etchant while we are working.

I'll bring gloves for anyone wanting to take part in the chemistry part of the project.

Rick

HF as part of etchant CP4 was what the early Bell Labs people often used to etch germanium surfaces to a shiny condition for point contact transistors. Remember that while they quickly described as-yet built bipolar and FET devices, they persisted with point contact transistors long after everyone else had moved on. They even build a computer of some sort with them.

CP4 is an etchant which will more rapidly etch defects in the Ge crystal, thus a smooth surface (locally) is where to put the points down.

Germanium is fragile compared to silicon and mechanical polishing introduced defects in the crystal that propagated a micron or more into the crystal. Thus, it was a good idea to etch crystals before fabrication (but not necessarily required). That takes an an isotropic etch. CP4 is not one of those.

I do not think we are dealing with anything that is not very superficial. The transistors have been at room temperature and the only elements that might possibly diffuse at room temperature are things like copper and gold which will all have been "gettered" out into the emitter and base metals, a very fortunate thing.

The etches I proposed are what I used in 1959 after a lot of experimentation with alloy junctions with the aim of getting good junction properties. I do not believe IBM was using HF containing acids in the clean-up of surfaces after alloying by the time these transistors were made, although we certainly had it in our chem hoods .. (not clean hoods!!!)

I will bring more documentation on Ge etching than you and I would ever like to fully understand. Much of the information is just an accumulation of etch formulations and without any particular science behind it.

At this point, I would avoid any etchant which rapidly attacks the emitter and base alloy metals. Those have been pretty well cleaned up by etching. These transistors passed test and were used in 701s, so we aren't really looking for an etchant which will remove much material at all.

Hopefully, one of these days I will find a copy of the IBM internal report we wrote up on germanium transistor technology in the mid 1960's when we ran a head to head program with a silicon IC team to see who could get the fastest speed. That will have further insight into etches for germanium. Those transistors were much more sophisticated and we managed to get measured 150 picosecond circuit delays compared to 250 for equivalent bipolar silicon devices.

Rick

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Meeting Notes?
    As per Constantin - "We were supposed to repair a selected and measured transistor.."

    As per Robert (June 12) ... " - so the IBM lab experiment won't be on for ~ 3 wks..."

1. The loopy behavior should disappear if we remove the moisture from the surface of the germanium die;

2. The characteristics of the restored transistor should look perfectly identical to those of a good, healthy transistor because nothing happened inside it or below its surface (my first model);

3. The explanation applies equally to the npn and pnp transistors, which eliminates the shortcoming of my first model, applicable only to npn devices;

4. We have an explanation for the wide disparity of the observe characteristics: the pattern of the "ponds" of water (clustered molecules) is different from one transistor to another one and the current flowing on the surface takes different path from one transistor to another one, depending on how and where these "ponds" get connected to promote current flow.

5. Based on observations the group has collected so far, the I-V characteristic of the external surface current has a threshold voltage, which remains to be explained. I can later propose a first-model for it.

IBM in the 1954 era had tried to get the big companies (GE, Westinghouse, RCA, and also the others entering the transistor business to design for low base resistance. Philco in their surface barrier transistors had the thinnest base and also a ring contact to it. The issue there was that the emitter and collector were etched into the die down to the thickness of the base region. Those were the best transistors of the time (later improved by "micro-alloy" and diffused base. Their problem was that the very thin physical base was also very fragile.

The transistors coming out of the group led by Dick Rutz were essentially the prototyes of the logic transistors used from the 1401 through to Stretch and Harvest, IBM's first supercomputers. They were definitely ring base.

Even once IBM went to silicon, their transistors had a single emitter stripe between two base contacts, again for base resistance reasons.

My belief is that conductive surface crud which connects to the emitter has the possibility of creating an inversion layer when the emitter is forward biased. That was discussed in a few articles at the time, but I have no idea where they are. In forward bias, as this built up over time due to the relatively high crud resistance. The inversion layer would emit minority carriers into the base increasing current.

When the transistor was turned off, the inversion layer would cut off from the emitter, but remain emitting until the charge had either flowed out by emission or recombination. This would be an intermediate time function.

This is a "switching" view of the operation and not a curve tracer one.

This phenomenon could have been similar for both npn and pnp transistors with different actual model parameters.

Most of these transistors were operated into saturated mode so that there got to be excess minority carriers in the base because the collector voltage dropped to where it wasn't as efficient at "collecting" from the base.

The excess emission into the thick regions of the base is one of the places that has to get swept out in turning off a saturated transistor.

The excess emission from the emitter connected inversion layer is in addition to the regular saturation recovery and should have different conditions. It will be slower starting and longer turning off.

Now I have gotten everyone confused, I will quit.

Rick

Rick's recollection that IBM's transistors had base contacts of either annular or 2-side stripe geometry excludes the possibility of extrinsic emitter-to-collector currents (my latest model). It also opens a new dimension in our space of loopy-transistor modeling: the physical construction of the transistor.

The model based on inversion-layer injection is attractive, but, if we see loopy behavior in both npn and pnp transistors, then we have to assume that the "surface crud" is positive in npns and negative in pnps... which is quite a strong assumption.

Anyway, we have too many uncertainties in our thinking and it is the time to eliminate those we can. In my opinion, there are two things we can do along this line:

1. Determine visually the geometry of the base contacts in the IBM 1401 transistors. These are huge devices by today's standards, the geometry of which can be seen with bare eyes or with a 10x magnifier. It only requires the transistor capsule to be open and can be done before the repair experiment. A camera-attached microscope would be a great "plus" for documenting this project. So far we have the pictures below, googled with "IBM 1401 transistors/images" and "Ge alloy transistors":
   
   
   
   
   
   
   
   

   The first three are exactly as described in Rick's recollection, i.e., annular base contact (see his name on the second one!) and the fourth is the one that confused me (lateral base contact).

2. Continue with the transistor repair experiment... This will determine (1) whether humidity or other type of external contamination is causing the "loopy" behavior and (2) whether the intrinsic properties of the device remain intact if the external contamination is removed.

Constantin

There may not be a need for a separate explanation for pnp vs npn. I'll try to get more coherent on this, but chime in as I try to think it through.

If the bare surface is something like mid-gap potential .. based upon the etch which left it in good electrical state, then one might view a "crud" layer on the surface which has a high sheet resistance, but which is electrically connected to both the base contact and the emitter.

Then, currents (charge) could flow into this sheet as part of a small parasitic emitter base surface leakage. If the sheet resistance is high, it could have rather long time constants.

Now to digital language. When the emitter is turned on, the surface potential near the emitter will be close to that of the emitter and a surface inversion layer might be induced. This also would be "connected" to the emitter and could be a source of additional injection of carriers into the base, increasing the collector current from that of a "good" transistor without this funny surface emitting layer. Similarly, when the transistor is attempting to turn off, the emitter will go to a low voltage (non-emitting state) and turn off. This voltage change will pinch off the surface channel at the emitter, leaving the bulk of the surface inversion disconnected and still in forward bias until the excess charge leaks off and equilibrates.

Explanations like this were what was talked about with leaky transistors. The explanation for the leaky silicon transistors due to etching off the top PSG oxide and unlocking the charged sodium ions (in my explanation of IBM's issues very early when it moved to silicon transistors.The mobile charge there was the sodium ions from fingerprints.

I've a couple of long airplane rides coming up soon. I'll try to have some recreational time thinking more deeply. I think we were into surface inversion phenomenon and the charge being driven by the emitter voltage.

Rick

This is the good news... The bad news is that it is essentially useless for our loopy transistors... The closest it gets to our project is at the beginning of Chapter 2 (pp. 27-36). See that, contrary to the tabloid descriptions, Shockley gives full credit to Bardeen's theory on surface states!

The book deals essentially with the theory of semiconductor devices, where Shockley was the first to come up with a manageable way of solving the pertinent equations (known before, but impossible to solve without computers). He used genially inspired approximations included in the so-called "Shockley's boundary conditions". Shockley's transistor theory was used thereafter in hundreds of books, most of them clearer than his original. For your information, Shockley's approximations, described one year before in a Bell System Technical Journal (the most important paper of semiconductor technology, after many authors) were confirmed by numerical calculations after about 15 years! Your book fully contains that theory.

For the Germanium era, I recommend Phillips (1962), and for the current times (Silicon) I recommend Grove (1968), followed by Taur-Ning (2009).

Coming back to our loopy transistors, I strongly recommend everybody to find a companion book in the Bell Telephone Laboratories Series, "Transistor Technology, Volume II", edited byF. J. Biondi, Van Nostrand, 1958. It is a collection of the most important original papers published after Shockley's seminal contribution. Chapter 11, "Design Implications of Surface Phenomena", contains 5 essential papers for understanding surface phenomena in Germanium transistors. Robert already has the first of them (Kingston). Their language is more familiar to Rick, who made Germanium transistors. I only used them... My loopy transistor model was based on Grove's silicon surfaces theory, which cannot be easily transposed onto Germanium...]

Finally, do we have an agreement on the forthcoming loopy transistors meeting?

Once again, congratulations!

Constantin

Executive Summary: Bathing a loopy Ge transistor in Hydrogen Peroxide vanquished its loopy IV behavior, confirming the hypothesis that it�s caused by some (still to-be-fully described) sort of surface contamination/effect.

1. In the previous week, I re-examined all eight known loopy Ge transistors on a Tek 7CT1N curve tracer and, since prudence suggested that we mess with just one of our gems,
   I chose one prototypical victim loopy transistor, labeling it NPN-2.

   Here�s its pre de-capping IV curve and 7CT1N settings, which imply a low Beta of ~16.*
   (Note that the horizontal scale is 0.5V per division in all of the IV curve photos until the last several and the vertical scale is given by the �Vertical Amps per Division� knob.
   The 7CT1N deploys a current source for the base current (when in bipolar mode, as here).
      

2. In the previous week, Mark refined the technique of de-caping TO-5 lids from two transistors using a vintage lathe in Almaden's machine shop.
   Here's Mark de-capping NPN-2 on Friday morning:
   

   Here are NPN-2�s alien-faced post de-capped portraits:
      

3. Here are the Loopy Ghost Busters (Mark, Rick, Constantin) reporting for duty in the Almaden �nano MRI� lab
   (a classy place � capable of measuring the spin of individual electrons or atoms!)
   

4. Here�s NPN-2�s IV curve after de-capping:
   (Unfortunately, I didn�t photograph the 7CT1N knob settings until after the next step :-(
   

5. Before proceeding to the surface cleaning experiment,
   Constantin asked to measure the IV curve with swapped emitter and base stimuli, which just rattled us/me:
   

   Re-measuring the IV curve with normal E-B-C connections,
   I noticed that its Beta was now (unexpectedly) low, ~ 1 (unity)
   and may have needed a higher base current to act like a transistor (miliAmps)
   Presumably its Beta dropped after the de-capping?
      

6. Here�s a photo of Rick bathing NPN-2 in a hot (~70 C) 30% solution of Hydrogen Peroxide (H2O2) for 2 minutes,
   and a post-bath photo of NPN-2:
      

   Two things were obvious on the curve tracer after the bath:
   It�s IV curve was still displaying some weird dynamic looniness
   and its breakdown voltage was much lower, only about 2V:
      

7. Rick thought it needed a kick in the pants, so he gave it a 2nd dunking in the H2O2 for just 15 seconds
   and then washed it with Isopropyl Alcohol. It still had a little latent looniness, but the Beta improved to ~5
   (the breakdown voltage was still about 2V):
      
   

8. Constantin decided it was still wet around its ears, so he drew his heat gun for a short blast (~5 seconds),
   which seemed to vanquish most (but not all) of the remaining loopiness:
      

9. On Monday evening, I re-measured NPN-2: its vacation in Palm Springs was good for it,
   as all signs of loopiness were vanquished and breakdown voltage was higher (>10 V):
      

10. I remeasured NPN-2 again this evening: the holiday break has been helpful too,
    with its Beta rising some more to ~10 and its breakdown voltage rising to ~14V.
    (Note horizontal scale is 2V/division here).
    But its curves aren�t as horizontal ...
       
    

- Robert <

p.s. For reference / sanity, here�s a perfectly good (de-capped, untreated) alloy junction NPN with a Beta >100 and breakdown of ~16V:
(Note horizontal scale is 2V / division here):

It�s interesting that even a good/healthy Ge transistor shows a little loopiness in the breakdown regime!

Thanks very much for this report.

I can contribute now with at least one discovery/interpretation, as follows.

Number One

When you swapped emitter and base terminals at the curve tracer, it continued to deliver base-current steps to the transistor. The transistor was now in the common-base configuration and needed Beta-times greater current steps, as for an emitter input, to display full-screen characteristics!

Receiving much smaller base current steps, the family of I-V characteristics collapsed (I remember that) and you increased the input current steps to get full-screen characteristics. Most probably, you increased the input current steps by a factor of Beta and left the curve tracer in that setting.

When Rick brought back the transistor from the second bath, the curve tracer was delivering large input current steps, as for an emitter current: each input current step was Beta times greater than needed for the common-emitter configuration. We all thought it was the normal setting (base current steps) we normally use. Therefore, we have to multiply the reported Beta reading of "1" by the scale factor of Beta, to get Actual_Beta = 1 x Beta = Beta, i.e., i.e., the original Beta of our NPN2.

I may be wrong again, but, please think about this...

Number Two

The common-base characteristics rattled me initially, but not now, after more thinking. Please see the attached slide,in which I am making sense of these characteristics.

There are five IC-VCB loopy characteristics, where the first one, at IE = 0, reaches a breakdown voltage VCB0 of ~ 18 V.

The other four characteristics do not reach the collector breakdown voltage due to the power limitation imposed by the curve tracer. However, each of them has a premature breakdown voltage at an increasingly lower voltage in points B through E as we increase the input (emitter) current. That premature breakdown must be local because the current increase it determines is only a finite step, as typically encountered in channel-resistance-limited local breakdown situations.

Of the five I-V characteristics, I outlined in dotted line characteristic #4. See that the previous characteristic, #3, was not able to return all the way to its parking place as the looping process was slower than the input step. The curve tracer spot caught up with the evolution of the IC-VCE point while the Base current was already at the value for curve #4. You may have a better English to describe this, but I am sure you will figure out what I mean.

Another observation on these characteristics is that the premature breakdown in increasingly stronger as we go to greater currents. See, for example, the current step E of the characteristic #5. Intuitively, I can say that this is a consequence of a stronger (lower-resistance) channel at large input currents.

The above does not imply that we understand the nature of the loopy effect, it only shows an interpretation of the puzzling common-base I-V characteristics.

Number 3

We missed the opportunity to exploit the advantage of having an open device: with such a device you can always get powerful insights into transistor physics by illuminating the junctions. This is my fault, as I was having a flashlight with me and forgot to use it!

Final Thoughts

I insist again on the idea of studying the common-base characteristics before the common-emitter ones. Also on the idea of studying the steady-state regime before tackling the hugely more complex transient regime. If the curve tracer we have does not have the necessary slow sweeping function, then the manual DC setup must be used with a plotter attached to it...

For publication-grade material (if we ever get there), we will need a good camera for recording characteristics and events. For the transistor physical structure we need a "macro" lens attached to the camera.

Thanking again for your report,

Constantin

PS - Attached are some of my photos taken at this first lab session.
           

and this fragment from somewhere

> If you still have the 7CT1N with you, and the necessary time to measure and record, then you need only connect the collector and the base terminals of the transistor as follows and plot the I-V characteristic at zero input current, with the common-emitter configuration of the 7CT1N unchanged: > > Collector of the 7CT1N --> to Transistor Collector > > Base of the 7CT1N --> no connection > > Emitter of the 7CT1N --> to Transistor Base > > (Otherwise, connect only the Collector and the Base of the 7CT1N if you change its configuration to "Common Base"). > > Ideally, we should have the breakdown characteristics of the healthy, loopy/capped, loopy/uncapped-fresh, and loopy/uncapped-treated transistors.

     Dr. Constantin Bulucea had various technical positions, from senior engineer to chief technologist within National Semiconductor (NS) between 1990 and 2011. There he conceived the process and device architectures for company�s 0.25, 0.18, and 0.13 microns CMOS processes, introducing the surface-channel CMOS technology with halo implants and retrograde well profiles. In 2011 he became a Distinguished Member of the Technical Staff of Texas Instruments (TI) as a result of TI�s acquisition of NS and helped company�s power group develop the trench FET process. Before joining National, he worked for Siliconix Inc, where he completed the development of industry�s first trench DMOS power transistors.

     Dr. Bulucea spent the first half of his professional career in Romania (1962-1987), where he introduced the new courses of Linear ICs and MOS Device Electronics, while having responsibilities in country's semiconductor industry, from device engineer to director of R&D. In 1978, he founded country's Annual Conference on Semiconductors (CAS), which later became an international IEEE event.

     Among his best-known contributions to the field are pioneering works on surface breakdown and hot-carrier injection in MOS devices (1974-80), the physical modeling of Nishizawa's Static-Induction Transistors (1985-1987), and the technology of asymmetric CMOS FIeld-Effect Transistors (2006-2010).

     Dr. Bulucea has published over 50 technical papers and holds 66 US patents. He is a Life Fellow of IEEE and a Honorary Member of the Romanian Academy. He has been an editor of Solid-State Electronics and the IEEE Electron Device Letters (EDL). He has also served on the Technical Committees of the IEEE Symposium on VLSI Technology and of the Bipolar Circuits and Technology Meeting (BCTM).

     Currently, Dr. Bulucea is a TI retiree and an editor of the IEEE Journal of the Electron Devices Society (J-EDS).

     Note � In 1969, Constantin Bulucea benefited from a Romanian Government scholarship (strictly limited to one year) at the University of California, Berkeley, where he got his second MS degree in Electrical Engineering. There, he was privileged to be taught by a unique group of renown educators and industry professionals including Donald Pederson (UCB), Bill Oldham (UCB), Jacques Pankove (RCA), Andy Grove (Intel), Rick Dill (IBM), and Bill Howard (Motorola).

THE “LOOPY” BEHAVIOR OF THE IBM 1401 GERMANIUM TRANSISITORS

A QUALITATIVE MODEL PROPOSAL

by

Constantin Bulucea

A reduced set of npn and pnp germanium transistors that failed to operate in 50-year-old IBM 1401 computers have been presented for analysis and device modeling. The devices in the set had in common (1) substantially reduced collector voltage capability, and (2) "loopy" behavior in common-emitter I-V characteristics as viewed on a Tektronix 7CT1N curve tracer (1978 plug-in module). The full set of defective transistors may have contained additional failure types, none of which were offered for consideration in the analysis. The investigation has been apparently motivated by the idea of qualifying the “loopy” transistors as memristor devices.

The “loopy” behavior of the IBM 1401 transistors was first revealed in the IEEE Solid-State Circuits Magazine [1] with an allusion to a possible memristor effect. Subsequently, a task force, formed from volunteer researchers Robert Gartner, Rick Dill and the author of the present proposal, was created and chartered with the investigation of this behavior, in close interaction with the larger IBM 1401 restoration team. This article reflects the current understanding of the electrical behavior of the “loopy” devices as seen by the author and not fully debated within the members of the task force.

Slide 1

The proposed qualitative model to be discussed here assumes (1) limited-area surface contamination with positive charges around the emitter-base and collector-base regions and (2) presence of surface states (a.k.a. “fast surface states”) over the same or more extended regions, as illustrated in Slide 1 for an npn device.

1 – Reduced Collector Voltage Capability

The reduced collector voltage capability (premature collector breakdown) of the “loopy” transistors can consistently be explained, for both types of transistors, considering the assumed limited-area surface contamination with fast surface states and positive charges around the emitter-base and collector-base regions.

In order to understand this model, the reader needs to get familiar with the basic theory of the influence of the surface fields on the breakdown voltage of p-n junctions and its associated junction breakdown-voltage collapse phenomenon.

Slide 2

The basic theory is included in Grove’s book [2]. Finer details of it are described in the original publication by Grove, Leistiko, and Hooper [3] and in the continuation work by Rusu, Pietrareanu, and Bulucea [4]. A visual summary of the breakdown-voltage collapse phenomenon is included in Slide 2.

The theory, developed and proven on silicon gate-controlled junctions, is perfectly applicable to germanium junctions, if the gate voltage is replaced by the fixed surface charge Q_S = C_S V_G, where C_S is the capacitance between the surface charges and silicon. The fast surface states, playing a minor role in surface breakdown, in comparison with surface charges, are neglected in the discussion below.

In pnp transistors, a strong positive Q_S creates accumulation over the n-type base region near emitter and collector (no practical consequence) and depletion and inversion over the collector n-type region near emitter and collector. The latter forces a contorted field structure around the collector-base junction, greatly reducing the breakdown voltage there, as illustrated on Slide 3. This junction breakdown situation corresponds to point 2 of the previously introduced Slide 2.

Slide 3 Slide 4

In npn transistors, a strong positive Q_S creates depletion and inversion over the p-type base region near emitter, extending the injecting area of the emitter [3]. On the collector side of the p-type base region, only depletion takes place, as the creation of an inversion layer is made impossible by the proximity of the collector-base junction, which diverts any generated electron toward it.

While depletion/inversion phenomena described above are well-known from the Fairchild Semiconductor literature collected in Grove’s book [2], the junction breakdown-voltage collapse happening in this case is relatively less known in the field. It was reported initially [3] as a spurious effect and later shown to be reproducibly and reversibly occurring in well-behaved devices. It was also demonstrated, by two-dimensional field calculations, to be the result of a switching of the breakdown location inside the device at large gate voltages [4]. This junction breakdown situation is illustrated on Slide 4 and corresponds to point 1 of Slide 2.

Our model assumes that, in “loopy” npn transistors, the positive charge around the emitter and collector junctions is strong enough to get the collector breakdown voltage collapsed to point 1 of Slide 2. With the same assumption of strong positive charge, in pnp transistors the collector breakdown voltage is reduced, by inversion over the collector region, to point 2 of the same slide.

According to this model, a wide distribution of reduced breakdown voltages is expected to be observed, corresponding to various levels of positive charge contaminations present in transistors. Moreover, major emitter-base or collector-base leakages are expected to be observed in devices having surface contamination spread all the way from the emitter or collector to the base contacts.

2 – “Loopy” Output Characteristics

Consider a “loopy” npn transistor with externally applied emitter-base forward bias and collector-base reverse bias, having the hysteretic common-emitter output characteristics illustrated in Slide 5 [1]. Unlike this one, healthy counterparts do not display any hysteresis during curve tracer sweeping with a typical 50/60 Hz sine or seesaw collector voltage.

In the breakdown portions of the displayed characteristics, the avalanche-multiplication collector current is a function of the electric field magnitude at the breakdown location which, according to Gauss’ Law, is a function of the electric charge density at the same location,

 = q (N_D – N_A + p – n),

where N_D and N_A are the donor and acceptor concentrations, and p and n are the hole and electron concentrations in the point where breakdown takes place. While N_D and N_A are fixed, p and n vary during collector voltage sweeping, increasing with applied voltage as the result of generation by avalanche multiplication.

Slide 5

As the voltage of the sweeping ramp returns from its peak value in point C, the avalanche generation of electron-hole pairs starts decreasing. In order for the collector current to return to the same value it had before in point B, the electric field must recover to the same magnitude it had before there. This only happens if the excess carriers generated by avalanche multiplication are removed faster than the ramp voltage returning to the value corresponding to point B, at V_CE1.

Avalanche-multiplication-generated carriers, approaching plasma concentrations, are removed by a complex combination of drift, diffusion, and recombination processes. In healthy transistors, this happens fast enough for the usual 50/60 Hz sweeping rate of the applied voltage, as demonstrated by their I-V characteristics not having loops.

In the presence of surface charges, collector breakdown happens at the far end of the surface depletion region, as shown on Slide 4, which brings the generated carriers in the immediate vicinity of the surface-state defects. The mobile electrons and holes can jump on the energy levels of the surface states toward a “stepping-stone” mode of recombination, usually referred to as “recombination through intermediate centers” [2]. This type of recombination is slower than the band-to-band recombination, happening in healthy germanium transistors, due to the finite times the captures and re-emissions of carriers take. In addition to this possible slowing down process, carrier removal by drift is also slowed down by the longer path of electrons to the emitter.

The delayed recovery of the electron and hole populations toward the direct-sweeping value in point B causes a delayed return of the electric field to the previous value at the same collector voltage, i.e., a higher field at the breakdown location. This, in turn, determines a higher avalanche generation of carriers and so a higher collector current in point D than in point B, resulting in the observed hysteretic aspect of the I-V characteristic.

In view of this model, the “loopy” aspect of transistor’s I-V characteristics is a signature of the presence of undesirable fast surface states in the device. A clean process, combined with a good, hermetic packaging, assures that surface states are below the limit for which they display “loopy” characteristics.

By the same token, it is to be expected that healthy high-gain (“super-beta”) transistors, having long recombination times, also display “loopy” characteristics in the incipient avalanche-breakdown regime. Conversely, a regular healthy transistor operated in the same regime should also display “loopy” characteristics when swept with very fast voltage ramps.

Independently of the presence of the surface states, the fixed positive charges assumed in this model extend the emitter area through the field-induced inversion layer. This increases the emitter current in contaminated devices with respect to the clean, healthy devices [5] (Rick Dill’s insight). This increase is permanent for a given surface charge distribution and is believed not to be responsible for the “loopy” behavior observed during sweeping the output characteristics. However, a side-by-side comparison of a “loopy” and healthy transistor should reveal increased emitter and collector currents in the former.

In proposing the model described here, the author is aware that this model can only stand as an unverified theoretical speculation with some finite chance to be true. A first verification of this model would require at least 2-D time-dependent computer simulations using programs like the Synopsys/TMA Medici, with the inclusion of postulated surface charges and states. Further on, a Ph.D.-level proof would require physical identification surface charges and states by independent determinations like capacitance-voltage (C-V) measurements, deep-level transient spectroscopy (DLTS), etc.

It is also worth observing that a quantitative analytical theory is virtually impossible due mainly to the complexity of drift and diffusion processes in avalanche-multiplication conditions and the two-dimensional nature of the geometries involved.

3 – The Memristor Illusion

According to the literature summarized in Wikipedia [6], the physical definitions of a memristor device as a two-terminal device are multiple and controversial. The idea of directly linking the electric charge Q with the magnetic flux, , through a new material property called “memristance”, M,

d = M dQ,

is unfunded in terms of classical electromagnetic theory: in electromagnetic theory, the magnetic flux is related to the current density, J, not to its time integral, Q (Ampere’s Law)!

In this confusion, mathematicians have taken advantage of the opportunity to introduce memristors as a class of mathematically defined devices through a set of differential equations.

Obviously, it makes no sense that our small task force of volunteers to dissipate its limited time resources trying to qualify the “loopy” germanium transistors as memristor devices, either physically or mathematically.

Even if the group succeeds in this dreadful mission, using carefully selected devices, reducing the discovery to practice becomes even more dreadful. The memristor property appears to be enabled by the existence of contaminating surface charges and states that can hardly be applied selectively for building miniaturized devices. In semiconductor technology, these defects have been minimized, by full-batch thermal processes, to levels that they have become irrelevant. Thus, intentionally re-creating the respective defects locally appears to be meaningless, if not impossible.

4 – Literature Findings

The literature on germanium surfaces is overwhelmingly abundant and complex. An excellent review is provided in Kingston’s 1956 paper in the Journal of Applied Physics [7].

There is virtually general agreement that positive surface charges are formed by air or moisture contamination on germanium surfaces. These charges create inversion channels on p-type samples, which have been the principal measurement vehicles in experimental investigations.

There is also very good agreement on the long-term reliability of germanium alloy transistors once they are well cleaned and hermetically sealed. The germanium transistors still functioning in the 50-year-old IBM 1401 computers are just another outstanding confirmation of this assessment.

Finally, a practical review on the chemistry of surface charges has been published by Wahl and Kleimack [8], with the interesting discovery that the moisture and oxygen contaminations have counteracting effects and usually combine to yield very good transistor characteristics.

5 – Project Closure Recommendation

Author’s recommendation is to close this project at the level of the proposed recommendations, as debated and amended among the members of the task force, with no further dissipation of research time. A publication in a peer review journal is not recommended as the proposed model is expected to be seriously challenged with requests for simulations and physical identification of the assumed surface charges and states. A brief communication in the IEEE Solid-State Circuits Magazine is still possible for the sake of closing the discussion on the “loopy” transistors started there, if resources can be found for augmenting the material with an experimental section and for the writing and drawing work.

References

1. R. Garner and F. H. Dill, “The Legendary IBM 1401 Data System Transistors”, IEEE Solid-State Circuits Magazine, Winter 2010.

2. A. S. Grove, “Physics and Technology of Semiconductor Devices”, Wiley, 1967.

3. A. S. Grove, O. Leistiko, Jr., and W. W. Hooper, “Effects of Surface Fields on the Breakdown Voltage of Silicon p-n Junctions”, IEEE Transactions on Electron Devices, vol. ED-14, pp. 157-162, March 1967.

4. A. Rusu, O Pietrareanu, and C. Bulucea, “Reversible Breakdown Voltage Collapse in Silicon Gate-Controlled Diodes”, Solid-State Electronics, vol. 23, pp. 473-480, 1980.

5. F. H. Dill, “Just Plain Alloy Transistors – IBM Style” e-Mail Communication to members of the Computer History Museum “Loopy” Transistors Task Force, March 2016.

6. Wikipedia article “Memristor”, https://en.wikipedia.org/wiki/Memristor

7. R. H. Kingston, “Review of Germanium Surface Phenomena”, Journal of Applied Physics, vol. 27, November 1956.

8. A. J. Wahl and J. J. Kleimack, “Factors Affecting Reliability of Alloy Junction Transistors”, Proceedings IRE, vol. 44, April 1956.

Sunnyvale, CA, 16 February 2017

"Great paper! It's very deep yet entertaining, unusual and anachronistic. I think after adding a grandiose (and possibly tongue-in-cheek) introduction about the world-changing implications of memristors, the restoration of the historic 1959 IBM 1401, and the serendipitous discovery of loopy Germanium transistors, it should be submitted for publication to the Journal of Irreproducible Results. Seriously. It's so good, I bet it could win you a trip to Stockholm and possibly a coveted Ignobel prize."

Marc

"This JIR listed �favorite article" is right down our area of expertise. I suspect JIR articles are better appreciated under the influence of something�. ;-)
http://www.jir.com/turboencabulator.html"
...

I did respond, but my response was simple. The "etch" we used was NOT CP4! It was 30% or so H2O2.

CP4 was used in early days and still later as a first etch for alloy junctions. There, it did etch the indium or tin (majority alloy materials in pnp or npn transistors) and cleaned up excess metal in contact across the junction(Shottky contacts) as well as etching the surface of the semiconductor.

CP4 fell out of favor as a final etch/surface treatment because it both etched the semiconductor preferentially making pits and also produced a high "surface recombination velocity" which caused minority carriers reaching the surface to be lost. I made some measurements of this in my PhD thesis.

Hydrogen peroxide was one of the etchants (cleaners) that left the the surface in a state which did not kill the minority carriers (very important in the unijunction transistors I was working on). It was also used on bipolar transistors for the same reason.

Peroxide does not etch the metals significantly, but it does clean up residue on the surface which may have free ions and cause surface inversion of the base. This would show up in a time dependent current gain of the transistor when turned on because the near inverted surface would become inverted and expand the effective area of the emitter at at low frequencies. On turn off, the response would also be slower because reversing the emitter bias would isolate the emitter from the surface inversion which would continue to emit until its charge died out.

I recall seeing a paper in the early days which described this cycle, but have absolutely no idea where to find it.

The transistors we worked on were "abused". We didn't have a microscope to look at gross deformation of leads or contacts to the alloy regions. I am not sure whether the changes that were induced were due to removal of contamination layer or mechanical abuse to the transistor in our relatively coarse experiment.

Since we didn't understand inversion layers (not yet having FETs), the physics was elusive and difficult to come by. A colleague of mine did investigate GE FETs after we abandoned our high speed germanium bipolar program, but I never saw any of his results. He was Hwa Nien Yu and worked at IBM Research in Yorktown, but I haven't been in contact with him since the late 1960's. He might well have done some key experiments because his work was after we had learned about surfaces from silicon.

I think we need to look at contamination as something not that far from sodiium in silicon oxide, but in a far less understood environment. It doesn't take a whole lot of ionic charge to widely swing the flat band voltage. This was something IBM learned without understanding it at the time from the tale i sometimes tell about the shut-down of transistor production in the first month of ramping up production of the new 360 family of computers and the discrete transistor SLT technology. IBM's phosphorus emitter diffusion was done by a phospho-silicate glass (PSG) layer deposed on the surface of the transistor over the entire surface and diffused the emitter from the places where this glass was deposited in openings of the oxide.

A month into production, a line operator over etched the wafers at the end of the process and removed the PSG overcoat which had served unknown to "getter" all the sodium ions into it and away from the surface. This is why IBM could make n-channel FETs later in a period when the rest of the industry had to eliminate all sodium from surfaces before every hot process. At the time this was discovered, it wasn't the physics that was understood, but rather the etch that made the transistors unstable (silicon free in the oxide) was identified.

I would be happy to get together again and look at some more transistors, but I hope that we can get beyond our first crude experiment which seemed to show that peroxide had made a bid difference in the surface .... if it wasn't something we did that day.

I have been very, very happy to get together with Constantin. He is someone I really admire and thing that his incites have been very important. In particular, I agree that if you can't draw the band diagram, you probably can't understand the problem. Perhaps the way to start is for Constantin and myself having some time to sit down and try to draw the band diagram, which is a big piece of how we learned about surfaces and surface charge.

BTW, Dick Rutz, who I worked for for several years in my early career, used to look at unexpected curves like the ones we are looking at and called them "hooiey wookey effect". He used that whenever some physicist, thinking they had discovered the "next big thing" and showed some funny IV curve that they would change the direction of mankind.

An adder is that he and I are on what was perhaps the most important patent of the discovery of the injection laser. We had both dropped enough GaAs wafers to understand that they broke along 110 faces. So, If you align the wafers appropriately, you can cleave them and get flat faces for the ends of the laser by simply cleaving the wafer with a razor blade. I was the one making the lasers, but he got his neme on the patent because we both saw how important it was and he got the crystals aligned for sawing.

Rick

p.s. Is anyone looking at TV screens? We are now into 4K at minimal additional cost. There is a "nano" approach to phosphors which is ending the short reign of "best screens". Interesting .. but there are also some new dimensions I'm not sure people understand. In addition to much better color and brightness range, there is clearly a 2-3x ability for power reduction for screens. I don't work for anyone who does patents any more, but the opportunity is there. (P.S. is this equivalent to publishing rather than patenting?)

R

      It is easy to imagine the designers/buyers/fabricators/... would have much rather cooled their magnets with cheap, easier to handle, easier to contain, liquid nitrogen at 77 K - about 40 times higher in temperature. - Unfortunately, the technology of this higher temp superconductor is not ready for practical use :-((

Starting e-mail of this thread

--------------------------------------
-------- Original Message --------
Subject: loopy transistors
From: Scott Dorsey < kludge@panix.com >
Date: Thu, August 30, 2018 8:07 am
To: ed@ed-thelen.org


I just came across your page about loopy transistors on the IBM 1401. I have
been working with the MP40 alloy transistors which were made in Russia at
what is now the Proton factory from the late 1960s until 1992, and every single
one of them exhibits this behaviour. These were sold as general purpose
transistors for many years after the west had abandoned germanium and alloy
construction.

None of this is as severe as the failed transistors you see, but the effect
is enough to be very alarming. Here is one photo:

RussianTransistorCurveTrace

I spoke with some of the Soviet folks who had been designing with these parts
and they just shrugged and considered it normal behaviour for them. Nobody
had been interested in investigating the issues.

I believe your description of contamination issues is correct and I suspect
cleaning them might also result in an increase in beta and possibly a reduction
in noise.
--scott

-------------------------------------------------------------------
I (Ed Thelen) forwarded the above e-mail to some more knowledgable folks.
Constantin Bulucea < constantin . bulucea @ gmail . com >
responded:

Dear Ed,

The I-V characteristics displayed by these transistors appear to be quite normal...
Their small loops may be curve tracer artifacts.
I remember that the Tektronix curve tracers had a knob for reducing looping.

...

From a brief Crete vacation, with best wishes,

Constantin

------------------------------------------------------
from Anonymous

diagram of Tek 177 Probe

Well, I need to ask a few questions first to Rick and Constantin. The Germanium NPN that was faulty looked peculiar under the microscope. Both of the solder blobs looked very dry, dull and grainy, and one of the gold wire bonds looked as if it was not even in contact with the blob anymore. It immediately reminded me of degraded tin metal that you sometimes see in vintage objects. Sure enough, this morning Ken brought to our attention an article written by Rick, which indicates that the metal dots in NPN transistors are Tin, with Antimony for the N doping. I proceeded to entertain the local crowd with a YouTube video from Cody's Lab, where he transforms shiny metallic tin into brittle grey tin and back (see here: https://youtu.be/ITgfscq6__A )

He also says that the Tin has to be pretty pure and pretty cold for this to happen.

Few questions:

1. were the diffused transistors made in one go, where the solder dots with tin and dopant where heated once, doing both the diffusion and the soldering to the gold wire? Or is it a two step process, first a diffusion of tin-antimony disc at high temp, and then a soldering of the wire with a preform of tin at much lower temp? The latter would seem more natural to me.
2. does it seem plausible to you that we are seeing degraded gray tin? If it is indeed tin, and it was rather pure, and given that it gets cold in Germany in the winter, then maybe it's not that crazy that this might have happened?
3. first I was thinking of resoldering the gold wire with a small preform of eutectic Indium or lead tin, as I have done many times on laser diodes, because it melts easily at such a low temperature. But that's probably not smart, as that would contaminate the transistors with p dopants. Or does it matter at all given the low temp involved?
4. What about just trying to re-melt the tin blob with a hot gun?
5. we might need forming gas to do this correctly. I suppose flux is off limits as it would contaminate the Ge surface?
6. have we just gone bonkers? I mean, even more than we already were?

OK .... are you ready for this?

I will start tonight and continue with additions over the next few weeks. Any reference to gray tin is nonsense, since that it a very low temperature crystalline form to tin. Calling the metals "solder" both totally misunderstands solder and more particularly totally underestimates the knowledge of binary metal interactions at the time when these transistors were built. I will start out with the "alloy transistors" such as the Raytheon CK722 and the GE 2N105, which were the first transistors I could afford as a poor student. Building a transistor radio out of 5 2N105 transistors was an interesting challenge, but that will be saved because it isn't key here. We wouldn't have the 1401 with its alloy transistors without this little bit of metallurgy. Since we were physicists, engineers, and tech savvy support people, we knew little more about metallurgy than we had to.

Max Hansen's book " Constitution of Binary Alloys" let us know what happened when we heated a small piece of a metal on top material in an environment where they would act like solder, but which gave us insight into what was happening. No I have never owned a copy, but I ordered a used one tonight for under $12. You can't get that, but you can get a "new" copy for a little over $4000.

The dynamics of "etching" in semiconductors depends upon materials and crystal orientation. In general, the slow dissolving direction in Germanium is the <111> direction or surface. I will leave it to you to figure out the details, but if the wafer surface surface has a piece of other metal on it and is heated above the eutectic temperature, it will dissolve the germanium up to the solubility of germanium at that temperature in the molten mound. Because of the slow dissolution , the puddle of metal will be close to flat on the <111> bottom and have angular <111> edges.

Now when you have gotten to the temperature you want, you have a pretty well controlled penetration into the germanium surface. Now when you cool down, the first thing that happens is that germanium is re-deposited on the crystal according to the solubility at that temperature shown by Hansen's curves. In the case of npn and emitter alloying, the tin is the carrier. The important material is the antimony (or possibly arsenic or phosphorus) that gets left in the germanium as it solidifies from the melt. The tin isn't important, but the n-dopant (antimony) has to be large enough to provide more antimony on the emitter side than there is p-dopant on the other side. If there is enough antimony, you get a good emitter.

NOW as things cool down more, you start finding places in the melt there the germanium solubility is too high for solution and participates of where the tin settles out. Finally at the eutectic temperature the rest of the melt all solidifies into a tin/antimony doped germanium micro-crystal mess mixed with germanium doped with tin/antimony. This leaves a messy grey surface, but it is just the contact. It isn't grey tin. There is no "solder at this point, although the leads in the 1401 transistors were held in the puddle and what came out of the heat step was transistors with the leads attached.

The base was attached with ring contact in the same melt cycle, but its melt metal was either tin antimony for npn or indium alloy for pnp.

Out of the heat process, the cooling through the eutectic rapid melt was messy. Lots of micro-crystals were initiated and the surface engaged with them. It took an etch after to clean this up so that the junction was not compromised. That usually was done by an etch which just cleaned a little off all or most surfaces. The allor metals would still look very rough from the micro-crystals, but the electric performance could be that of the transistor and not alternate paths.

OK, all of this is about NEW transistors. Well that is what we started with. The general path was to get the transistors working as expected (performance according to theory) and then to seal the against moisture and mess of the future. This was the best we know to do and it worked remarkably well. Plastic encapsulated transistors failed early until there was a solution found by San Jose IBM chemists which allowed the plastic pack ICs we see today. When the hermetic seal breaks, then you have chaos. This happened with vacuum tubes (glowing as they did their business) and in out 1401 devices when either the solder seal failed or the iron in the invar leads rusted away.

Once the seal fails, the transistors are like the ones we built back in the 1950's Most of those processes are fairly "thin" surface issues that mess up the junctions by extended surface inversion regions where we weren't supposed to have them.

The NEXT set of comments will come after I get m personal copy of Hansen. It's been a LONG TIME. I suppose I can continue on about diffused base transistors. After summer in 1954 at IBM, I was at RCA Sarnoff Lab at Princeton in 1955. That is when Herb Kroemer arrived, having published the theory of the diffused base {drift) transistor shortly before. I was able to get a few of the transistors from the stock room, and they were capable in incredibly higher speeds. Everyone appreciated Kroemer (including the Nobel judges). Later at IBM I was asked to review a patent by Lloyd Hunter which was issued. It described using a diffusion to make the base region and lower concentrations on the collector side to allow higher collector voltages. It is the structure patent for Kroemer's theory.

Both Kroemer and Hunter played roles in who I am. An hour with Kroemer when I was having difficulty pulling together my PhD thesis gave me the key physics I needed. Note that I really didn't have a thesis adviser because no one in the department had ever worked on semiconductors. My stand-in was the department head Rod Williams, an amazingly good communications engineer, but no help with the technical details. Hunter came back into my life when I spent a couple of quarters teaching at Berkeley. He was at IBM San Jose on sabbatical from University of Rochester. He taught both me and my new wife to fly and love doing it. It was in gliders at Livermore, of course.

SO don't think that tin alloy materials should look like tin solder. The same for indium, but it never looked all that shiny. We learned a lot quickly and alloy transistors had melt puddles that were terminated by composition (alloy source plus dissolved germanium), temperature (which set how much germanium dissolved), and careful crystal alignment. In that same era, crystal perfection was increasing by leaps and bounds. It really didn't get all the way there until the DRAM era.

Rick

..... contact me directly if I have BIG ERRORS. I started out with dislexia before that was a diagnosis and have usually had to think differently. Out of that, I proof-read poorly.