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A Selection of 1401 Documents

text and images provided by
John Pokoski

Also a Question & Answer session about ALDs (schematic diagrams)

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Each document image is about 70 K Bytes
Sorted in rough chronological order.

5 more documents added Mar 09, 2009

Punching the clock. I recall that my class of new engineers (about 24) in 1959 raised a fuss about being required to punch a time clock, feeling that it was unprofessional. I could tell that management was concerned about an uprising. Finally, the rationale given was that IBM produced time clocks and it would be unseemly if its employees didn't use them.
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Early Underwood memo simplifying machine. Note that memo is to SPACE file.
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Good record keeping was essential to the development of the 1401. Changes could be instigated during normal working hours by engineers in the office as well as by engineers in the lab next door debugging the system at 2 AM. It was imperative that there be only one "golden" set of records and that the format for changing them was uniform. This led to these very specific rules. (For example debuggers could not just rewire a gate ad hoc to fix a bug, but must formalize it into an official written wire list change from which the corrections were made. This helped insure there were no "typos" on the wire list. At the same time the DVL's had to be updated in the correct colors and initialed and dated.) People followed these rules to a letter, not only to avoid the wrath of the bosses but to avoid the wrath of other engineers who might have wasted a lot of time due to improper documentation. Word quickly spread, and no one wanted to be the dolt who slowed development. Fred Droege was in charge of this unglorious but critical task and did an excellent job, being firm yet cordial.
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This is the earliest organizational chart I had. It was from just before my joining the company. Although it is dark, I noticed that on this one and others, the ability to read it is greatly enhanced by magnifying the screen.
Key words: Technical Responsibility 1401 Tape Edit System
"org chart Apr 59"
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This is a two page memo from Fran which illustrates a bit how he kept the pressure on to reduce hardware costs.
Key words: Card Count Down
"cheap May 59"
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Underwood memo regarding compare circuit. Pencil modifications on logic diagram due to Farbanish, who implemented it.
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Fran Underwood memo giving early definition of Model I and Model II machines.
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Russ Rowley memo about records.
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Underwood memo deleting "blank column test" function.
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Underwood memo regarding printer carriage control.
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Op code modifications. This is one of many memos (mostly from Fran Underwood or Russ Rowley) making minor modifications to future engineering models as more was learned from debuggers, programmers, R&S people, Product Test, etc.
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Underwood memo regarding recomplementing. Hand notes are Farbanish's.
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Suggestion for a reset button.
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This is a typical memo regarding nomenclature. I included it mainly to show Fran's glorious signature.
Key words: Transfer to Branch
"T to B Jul 59"
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Early Fran Underwood memo describing interface to bank sorter/reader. I know this was completed as I saw the system run at a banking show in Chicago.
2 images
This is ... a nine page memo from Jim Ingram in 1959 describing the various machine models and options. It may be one of the more comprehensive of the various memos. The first page also has a long distribution list illustrating the people involved.
"models Aug 59"
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A memo from Jacobs to Ingram regarding terminology. Also note wide distribution list.
Key words: Print Buffer - Storage, Tape Attachment - Tape Input Output Adapter
"terms Aug 59"
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A two page memo about what I recall as "design automation" not "designomation". This involved the engineer drawing the design, including circuit and pin assignments on large "vellums". (Many such pages of logic were needed to complete the whole "gate" on the machine.) These would be translated into computer punched card format by several girls in the department and in the design automation group in another building. A program would then print out blueprints of the logic for the whole gate as well as check for overloads, mistakes in pin assignments, etc. After necessary corrections were made by the engineer and helpers, it was run through the computer again. When it was all correct, the resultant pages were "masters" and the computer generated a "wire list" for the Gardner-Denver machine to wire-wrap the back of the gate. Engineering changes generated by debugging during testing were incorporated in red pencil on these masters. When the whole gate worked correctly, a final run through design automation was used to generate new masters and a final wire list.
"designomation Aug 59"
2 images
A typical memo.
Key words: Error Stop Error Reset I/O Check Reset
"errors Aug 59"
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A typical memo. (Two images.)
Key words: Machine Stop Machine Reset
"stop Aug 59"
2 images
A typical memo. (2 images)
Key words: Unconditional Transfer
"branch Sep 59"
2 images
... I think is my first engineering memo. It describes a multiply operation. I actually scanned this from the original ditto master which I had. The drawings of number fields were done by Fran Underwood, who supervised me closely. We both knew that his penmanship was better than mine. (Although I found that mine wasn't bad at the time.) Also I noticed several scissors holes where the secretary had snipped out typing errors. That led me to ruminate a bit. In all these memos, I saw no spelling or grammar errors. Nor were there any typing errors. Yet at that time there were no word processors nor spell checkers. Also no copy machines other than ditto machines and large blueprint machines. That meant that all these memos were typed on ditto paper, which is impossible to make corrections on. Thus each memo is a perfect draft. Maybe it is not an old man's imagination that people could actually write correct English in those days and that people could type quickly and accurately. And that they demanded perfection.
Key words: Extended Arithmetic
"multiply ex Oct 59"
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Walt Schaffer's memo describing the new Rewind and Unload instruction.
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This is a Reliability and Servicibility request. The response is tallied in Nov 59. I have many such requests, some involving minor logic and/or delay savings. They seem to originate with either H (I believe Harvey) Morrow or Tom McAdon of R&S. They are routed to Jim Harvilchuck who must have been the interface with R&S. Harvilchuck would then route them to the appropriate person. For processor stuff it was apparently Walt Schaffer. Walt often routed them to Paul Farbanish to respond. (Jim and Paul were Associate Engineers and Walt was a Staff Engineer in these early days.) I have several such pairs of memos but some are lengthy and faded, so I won't bother with them. You get the idea.
4 images
Edge connector slots to send signals between gates were at a premium. Sometimes they were routed through "feedthrough" gates on edge connector cables that had spare signal wires. This memo describes the documentation.
2 images
There was usually a slight tension between Product Test and the development engineers. PT's purpose was to make sure that the system met specs and would work reliably in the field as promised. The development engineers felt that their design was excellent and were concerned about keeping on schedule and keeping costs down. It was a healthy way to try to ensure a good system was delivered, in my opinion. This must have been an important memo, judging from the distribution lists on the first and last pages.
11 images
Description of "compressed word option".
4 images
Bespalko memo describing the various fields for division.
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Response to October R&S request.
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Earl Bloom's memo shows how he calculated the multiply/divide times on the old system. (not released)
5 images
Walt Schaffer's description of the P Op Code. (Special Move)
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Reliability and Serviceability suggestion from McAdon through Harvilchuck to Schaffer.
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This is my description of divide in December 1959. I just can't remember if this is the "original" or the "revised" version. The date is at the transition time. The beautiful hand printing on the second from last page is Fran's. I wouldn't be surprised if I had asked him to do it just to add a little class to the document.
11 images
Teaching assignments for 1401 classes for customer engineers, etc. Classes were in the "education building" in downtown Endicott.
"classes Feb 60"
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This gives an idea how three shifts were organized for testing.
"shift sched Mar 60"
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Hanf memo describing "new" divide addressing mode. Again, I am somewhat befuddled as to timing, as the revised divide was already debugged and working the previous December. Maybe further approval was required since manuals etc. had to be changed.
"div Mar 60"
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Multiply/Divide format. Bespalko was the primary designer of the "revised" system that went into production. Tom McAdon was from "Reliability and Serviceability". People from this group were attached to the designers, especially for the second model, as I remember. Their purpose was to help insure that the system would be reliable and serviceable in the field. Fancy that! Designers occasionally regarded them as a pain in the ass because of the additional cost and complexity of the changes they suggested. Minor squabbles often occurred, probably a healthy thing. I had no problems, particularly with Tom, whom I remember as a sincere, nice guy. I don't recall Smith. Note the quick response to Hanf's letter.
"md Apr 60"
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This memo is quite faded and the paper is dark. Magnification helps greatly. Bespalko gives a Boolean description of the revised M/D system. The pencilled questions and corrections are mine. The chronology of this befuddles me a bit as the system was already debugged the previous December. Maybe it has to do with a later repackaging for production.
"md bool Apr 60"
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Included for distribution list.
"tape May 60"
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... organizational chart from 1960.
"org chart May 60"
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Steve Bespalko's functional description of revised multiply/divide system.
6 images
Ingram memo on nomenclature.
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My memo showing hardware savings of new M/D system vs. old.
"MD comparison Jun 60"
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can't figger why poor lil ole me got a special invite to this class.
"olap class Spr 61.pdf"
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This was a hot issue that went right to the top. I remember working with Ahearn on it. There was a problem addressing 64K because of the limited number of alpha bits available. (Three digits allowed for each address. Middle digit used its two alpha bits for indexing. First and last digits used their four address bits (two in each digit) to expand address space. Thus the three digit address space (1000) could be easily expanded to 16K using the four alpha bits (a and b in each character.) 64K was a different matter. I don't recall what we did and I refuse to read it again. I'm retired.
"64K study Feb 61"
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Customer engineers were obviously having trouble servicing the very first machines in the field. (2 images)
"service info Mar 61"
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Walt Schaffer's early description of the proposed overlap feature.
"prop olap Mar 61"
3 images
Here is the "sterling" assignment that I mentioned in my book. Note Lloyd's of London mention.
"sterling Mar 61"
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Earl Bloom's second level logic diagram of part of process overlap. Pencilled notes mine. Undated, I guessed spring 1961.
"olap 2lev Apr 61"
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The author and the date of these overlap timing charts are unknown,
"olap tim cht Apr 61"
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Overlap time savings. No author, no date. Probably Earl Bloom in the spring of 1961.
"olap time Apr 61"
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Ingram comments on 1401 customer conference.
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Request for diagnostic programs for process overlap.
"olap diag 1"
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Response to request for overlap diagnostics.
"olap diag 2 Aug 61"
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This memo indicates the complexity and messiness of "process overlap".
"overlap Sep 61"
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"Clock Control and Delays - Stage 2"
"timing Sep 61"
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Here is a lengthy, detailed description of process overlap. It is undated so I gave an educated guess at Sept 61. Funny, but even though it appears to be the defining document, I don't remember writing it. In fact, it appears that I was an "expert" on overlap, yet when I was teaching computer architecture a mere eight years later, I didn't even use it as an early example of "direct memory access". From what I hear, this document may be important to the CE's at the museum. (I hope no one outside of IBM sees it, as it is labeled "confidential".) :-)
"olap Sep 61"
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Sequence of three memos reporting right to the top regarding compatibility problems. I believe Scott was division director, and Haanstra was his head of engineering.
"compatibility Sept 61"
Note the sequence:
- the top (first) could be labeled "the edict",
- followed by "the command",
- and the last (bottom) is "WHEW". ;-))
3 images
Two page memo regarding the customer engineering panel.
"ce panel Oct 61"
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Overlap items for inclusion in the 1401 reference manual. (I was curious as to whether these paragraphs were actually included, so I dug out my old reference manual. Alas, it was dated "major revision Sept 1961".)
"olap ref man Nov 61"
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Final decision on CE panel.
"ce panel Nov 61"
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Ken Bell's final report of the overlap serviceability committee.
"olap serv Jan 62"
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"hypertape Feb 62"
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This is a memo from a tester at the Endicott factory who went to Minneapolis and Detroit (as I did) to install process overlap in December 1961. Notice the Swedish names in the Minneapolis office. (My wife was a Swede from Minneapolis.)
4 images
A memo regarding hypertape. I spent a month in Poughkeepsie learning about hypertape. I don't remember anything about it now, even whether it was or wasn't eventually connected to the 1401. I transferred to a new assignment soon after this. I also got married that month.
"hypertape Apr 62"
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Walt's study of I-O delays.
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A study of clock and I/O delays.
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Request for hypertape info.
"hypertape request May 62"
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My response to the request for hypertape info.
"hypertape response Jun 62"
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Question & Answer session about ALDs - "schematic diagrams" from Robert Garner, Feb 22, 2009

John, Jud, et al,
Thanks again for the period design memos!

They reminded me that I've been harboring some 1401 design related questions that I was hoping you guys could help answer.
Question from Robert Garner Answer by John Pokoski
(1) In your ALD flow description ( ) , you wonderfully describe the new ALD flow as being introduced in summer of 1960.

If it was that late, how were the 1401 schematics done before ALDs, in 1958 - 59?

And how were the schematics mapped into SMS cards, gates, backplanes, cables, etc?

I hope that I didn't imply that ALD's were introduced in 1960. They were being used when I came on board in '59.

The decisions as to what logic was on what gate were made by the design engineers ahead of time. As the design moved through Design Automation and some gates became crowded, decisions sometimes had to be made to place part of a logical unit on a different gate that had some empty slots. This was not good because it required more cabling with associated space, delays, etc.

The engineer/designer went from a hand drawn "Second Level" logic diagram that showed basic logic flow to a "vellum" which was also hand drawn but on a standardized sheet that had fixed positions for logic gates as well as wire connections.

All inputs from other logic sheets in the same gate or edge connectors from another gate came in at the left. All outputs went to the right.

The designer kept track of the cards and gates on the cards by hand at first, marking them on the second level and then transferring them to the first level vellum in a specified format. The vellum was encoded by hand by girls into punched cards I think.

The cards for a gate were then run through a computer program which checked connections, loads, etc. and tabulated errors for the designer. after corrections and another "run" or two, the final version and the wire list was generated.

(2) How did you do static timing analysis? I assume problematic long paths were hand calculated? Did the ALD software ever assist with timing analysis? . Yes, I remember hand calculations and no help from ALD here.
(3) What were (are) the critical timing long paths in the 1401? Were there one or two long paths (STAR related) or hundreds? ;-) (This might help us verify the quality of clocks and signals related to most critical paths. ;-) Did you have any special (derogatory ;-) names for long/critical timing paths? I used to know this but forgot. No special names that I remember.
(4) Approximately how many timing problems were found during bring-up/ Model A debug? How many logic design bugs? How did you make changes in the lab? Model A debug was mostly before my tenure, but I am sure there were many timing and logic problems.

M/D was first done on Model B. It was complex and used a whole gate. I debugged it but my guess of twenty engineering changes is very rough. Remember that "SINGLE CYCLE" operation as well as odd field sizes caused special problems which were difficult for a designer to foresee.

(5) How was the cycle time of 11.5 microseconds decided upon? Was it 11.5 usec from the very beginning of the project? Before my tenure. I think it was related to the core memory speed.
(6) Did you find the alternating U/T levels of CDTL to be useful or a pain-in-the-butt (i.e., you had to inconveniently convert between U and T levels without logic)? It was a pain. Sometimes you needed a U level of a signal and only a T level was available. Thus a logic block (with associated cost and delay) had to be added to convert the signal. I can recall designers calling from desk to desk such things as "I need ten units of a U level of clock 030-060. Can you afford it?"

But this really wasn't a bother to me, especially at first. I was so green that I thought all computers were like this.

(7) About what percentage of the SMS cards were "stock" designs (from 7000-series) vs. entirely new designs, just for the 1401? Don't know.
(8) Were the magnetic core drivers in the 1401 memory circuits unique/ first with the 1401? Don't know. (As an aside, somewhere on the site I read a CE's memories of 1401 school. They were quite funny. I may have taught him in that class. Anyway he had a funny story about the memory designer. That would probably have been Tom Cooper and the story fit my memory of Tom perfectly.)

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