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A developing IBM 1410 FPGA implementation
- a switch converts a 1410 to a faster 1401

from Jay Jaeger < cube1 @ charter dot net >
Sun 5/2/2021. 4:21 PM
Re: Fwd: [Fwd: IBM 1410 FPGA Implementation Update - new github repository]
To: Rober Garner, 1401 Team
Cc: ... many others ...

Thanks for the shout-out, though three years in, I think I am a bit past
"begun".  ;)

BTW, because the 1410 had a hardware 1401 hard-wired as part of it (it
could emulate a 1401 with the flip of a switch that caused its logic to
become a 1401, albeit with faster core and different timings), when I
get done I should also have a 1401 as it was implemented on the original

The technique and application I used to capture the ALDs should be
applicable to most, if not all, SMS-based machines of the era.  I did
look at some 1401 drawings to try and generalize the ALD data capture
app some, as well as looking at the IBM SMS packaging document and
relying on some memories of how the IBM 7090 and 7094 were set up with
respect to machines, gates, panels, etc. though I would also not be
surprised if a source code "fork" or fixes/additions were required to
the application.  It might also be challenged by the speed of the ECL
based machines because of how it handles latches and triggers - it needs
the FPGA clock to be several times faster than the system clock,
depending upon how many latches and/or triggers are lined up in sequence.

Finally, I also posted the source (Borland C++) for my 1410 simulator on
Github as well at

BTW, my collection also has a recently resurrected Sun 4/60 Sparcstation
1 running off of a scsi2sd SCSI stand-in, though finding the mouse pad
for it is proving to be a challenge.


On 5/2/2021 5:47 PM, Robert Garner wrote:
> FYI, Jay Jaeger, a long-term correspondent with our CHM 1401 restoration 
> team, has begun to implement a 1410 in an FPGA.
> (following up on his earlier 1410 cycle-accurate simulator...):
>> Begin forwarded message:
>> *From: *Van Snyder > >
>> *Subject: **[Fwd: IBM 1410 FPGA Implementation Update - new github 
>> repository]*
>> *Date: *May 2, 2021 at 2:32:43 PM PDT
>> *To: *David Troendle >,
>> Ken Shirriff >,
>> Carl Claunch > >, Stan Paddock
>> >, Robert B
>> Garner >
>> -------- Forwarded Message --------
>> *From*: Jay Jaeger via cctalk > >
>> *Reply-To*: Jay Jaeger > >, General Discussion:
>> On-Topic and Off-Topic Posts > >
>> *To*: General Discussion: On-Topic and Off-Topic Posts 
>> > >,
>> General Discussion: On-Topic Posts > >
>> *Subject*: IBM 1410 FPGA Implementation Update - new github repository
>> *Date*: Sun, 2 May 2021 15:38:33 -0500
>> The last 12 months I have been pretty busy working on my 1410 in FPGA
>> project, and there is now more to share, though I have not done much
>> actual work since February - been too busy playing with other "toys".  8D
>> First, I finished working through all of the IBM 1410 and IBM 1415
>> Automated Logic Diagrams - generating VHDL and testing the results with
>> test benches.  [Note that this includes the built-in 1401 compatibility
>> mode, activated at the flip of a switch.] That took most of 2020.
>> So, the CPU generation in VHDL is now more or less complete, and I added
>> a hand coded memory module for memory, as core is kind of hard to find
>> on an FPGA development board.  ;)  I am currently using a Digilent Nexys
>> 4, but I think it might have even fit on a Nexys 2 - there is plenty of
>> room to spare, and there isn't anything in the VHDL aside from, maybe,
>> the memory implementation (though even that is pretty generic VHDL).
>> With this the CPU runs, at the very least, Unconditional branch (Jump),
>> Halt, NOP and Set Word Mark instructions seemingly correctly - I haven't
>> tried any others.  Somewhat surprisingly, aside from issues with the
>> hand coded VHDL in triggers and the need to communicate pins tied to
>> logic one or zero, the auto-generated VHDL works untouched.
>> I have updated the github repository for the C# database application
>> that generates the VHDL from time to time (and which includes the
>> complete database) at
>> There is now a *new* repository,
>> which holds the generated VHDL, some hand coded VHDL modules for certain
>> SMS cards (typically for triggers, for example), the console and test
>> benches I used along the way, and VHDL "Integration Tests" which are
>> designed to be loaded onto the board - the current one being
>> IntegrationTest3.
>> There will be, eventually, a third repository which will contain the C#
>> code that "hosts" the IBM 1410 console and peripherals, communicating
>> with the FPGA over a high speed serial over USB connection.  I figured
>> out that this should allow me to emulate peripherals without having to
>> resort to sending data over Ethernet, SPI, I2C or the like.  I have just
>> started that, so it really isn't at a point that there is much to share.
>> Once I have a console working (which will require a re-do of the console
>> VHDL implementation, which right now communicates in ASCII, but should
>> probably be using BCD), I should be able to pre-load into memory some of
>> the CPU diagnostics, by loading a diagnostic routine into either my 1410
>> simulator (
>> ), or Richard Cornwell's
>> emulator in SimH and then taking a snapshot of "core" to pre-load into
>> the FPGA.  At that point I expect I will be able to test the CPU pretty
>> thoroughly.  I hope and expect that will happen this year sometime.
>> Unfortunately, I do not have the ALDs (Automated Logic Diagrams) for the
>> IBM 1414 I/O Synchronizers, but I do have the Instruction Logic Diagrams
>> which should allow me to code VHDL to emulate card, tape and maybe
>> eventually even disk functions, so those might take a while.
>> If anyone cares....   ;)
>> JRJ
>> Begin forwarded message:
>> *From: *Jay Jaeger >
>> *Subject: **IBM 1410 software (Re: IBM 1620)*
>> *Date: *March 16, 2017 at 7:37:07 AM PDT
>> *To: *Robert Garner >
>> FYI, regarding IBM 1410 emulation (PR-108/PR-134/PR-155), I wrote a
>> cycle-level simulator, based on the CE instructional materials, some
>> time ago that successfully runs PR-108/134 and PR-155, but I never
>> released it.  (But if anyone wants a copy, let me know - it still runs
>> under Windows 10).
>> Subsequently another person, Richard Cornwell, has also written one,
>> with the goal of being part of SimH.  Last I heard, he was working with
>> the current curator of SimH to get it included.  He was also working to
>> include aspects of the IBM 7010 in his emulator, but the amount of
>> documentation on the extra features in the 7010 was not complete, last I
>> knew.
>> Tape images of PR-108 (which *might* actually be PR-134, with disk
>> support, but I don't remember for sure, and it is a while since I played
>> with it), PR-155 and some diagnostics are available on Paul Pierce's web
>> site, at
>> PR-108 (Maybe PR-134) is labelled "1410 Autocoder System Tape"
>> PR-155 tape images are labelled "PR155 from Tulsa" and "Master PR-155"
>> I also noticed references to doing a logic level simulation of the 1620
>> in the email thread.
>> My current project regarding the IBM 1410 is to take the Automated Logic
>> Diagrams and translate that information into VHDL.  This is a huge job.
>> So far I have entered the information from the ALD Circuit Card Location
>> charts (which, unfortunately, had a sheet or two missing, and are at
>> varying ECO levels) and am well along the way at analyzing the
>> individual SMS circuits into logic equivalents.
>> Then comes the enormous job of going through the ALDs page by page,
>> reconciling/comparing them against the circuit card location (I already
>> know there are inconsistencies) and developing a wire list, testing
>> individual sections, and putting it all together.
>> I just wish there were a way to get at the original files that were used
>> to produce the ALDs, as that would make things much much easier.
>> Unfortunately, the current IBM archivist has not responded to my emails,
>> not that it would be likely that such files would still exist anyway -
>> but there was at least some hope.
>> JRJ
... deleting a long history of e-mails going back to 2017 ...