return to main page

Weird Parts
(Strange voltage/current diagrams)


Serious papers


NOT Weird Parts, but some fascinating bios

in 2005

Ron Williams and Bob Feretich currently find the failed logic cards in our 1401. They then replace the card (we have spares for most of the popular SMS cards in the processor) :-))
They then write up the defect as completely as practical down to the pin on the suspect SMS card.

Tim Coslet is the person who fixes most of our (1401 Restoration) defective SMS cards. His primary aid is an in-circuit tester that he built from plans in the magazine ???. The write up from the trouble shooters speeds his search for bad parts. Tim, using his in-circuit tester, can get a good idea of circuit dynamic characterists with out unsoldering the parts for individual testing - a good thing! (After a part is really suspect from the in-circuit test, it is removed for individual testing and replacement.) The source of the problem is usually:

Tim then replaces the defective part from components usually purchased locally, and verifies that the performance of the circuit is better - again using his in-circuit tester. He then marks the replaced part with a red dot - to show the replaced part, and returns the fixed SMS card to spares.


Using the in-circuit tester is not as straight forward as individual component testing - being an acquired art - but does speed diagnosis and reduces damage to parts and SMS card traces. :-))

(There have been thoughts of making SMS card testers and test programs. But with about 120 SMS card types and several circuits per card and several tests per circuit - this would be a non-trivial task.)

Tim's in-circuit tester
Notice on the left that the driving frequency is 60 Hertz, power line frequency - much lower than the service frequencies.
- Tim's test probes are marked "Collector (Black)" and "Emitter (Red)" in the diagram.
- The outputs from this circuit "Horizontal" and "Vertical"
are fed into the x and y axis of an oscilloscope that Tim brings with him.
And a switch selection of resistors can help determine if the beta (current gain) of a transistor is

- above or below 50
- above or below 100
- above or below 150

At the test frequencies and the resistances involved, the capacitors are practically open circuits and inductors are practically short circuits. These "reactive" components should not make phase changes (loops) in voltage vs. current curves at the much lower test frequency compared with the service frequencies.

A person expects straight lines from resistances, and sharply bent lines from transistors and diodes.

And on good boards, the above expectations are met - the expected patterns on the oscilloscope are actually seen. :-))

But the world is a strange place. Many of the circuits reported bad by Ron and Bob give very unexpected patterns.

Comments by Tim Coslet
Looks like one of the Beta settings to me. The Beta of this transistor is close to the selected value, but it is leaking bad when reverse biased.
Looks like E-B to me.
Looks like C-B to me.
Looks like O-B to me.

We are at a loss to explain these loops. (Thermal effects seems unlikely to provide this level of change??) Please send suggestions to Ed Thelen ed@ed-thelen.org and Tim Coslet

Added Feb 23, 2006


Further details by Tim Coslet - Feb 23, 2006

The original design in the magazine used +-1V peak to avoid possible damage to semiconductors during in circuit test, but this is too small to turn on darlington transistor E-B junctions so I increased my design to +-2V. I also added a +-10V peak range to check reverse breakdown, low voltage zeners, and operate transistors at higher voltages. All the 1401 testing has been done on the +-10V range, as this seemed more "realistic" to me and I was having problems getting good Beta estimates on the +-2V range (due to an effect mentioned below almost all the transistors read very low Beta on that range, but more normal Beta on the +-10V range).

The scope was not set to 1V/div. I usually use 0.5V/div when using the +-2V range and 2V/div when using the +-10V range (so the curve fits the screen better). Unless I need to determine transistor type (Si/Ge) or breakdown voltages I'm more concerned with shape than exact voltage/current levels.

E-B is the Emitter-Base junction with the Collector shorted to Base.
O-B is from Emitter to Collector with the Base not connected (open).
C-B is the Collector-Base junction with the Emitter shorted to Base.

These are standard test definitions given in datasheets that I wired into my switch, so that I would not have to keep swapping leads around.

The Beta settings use an additional similar resistor network to inject current thorough the Emitter-Base junction while the main circuit is measuring the characteristics of the Emitter to Collector path (similar to the O-B measurement, but with the Base connected instead of open). The difference in the additional similar network is that the 1K resistor is replaced by a Beta*1K resistor (50K, 100K, and 150K in my box) and there are no scope connections to that circuit. To a first approximation, if the resistor selected exactly matches the Beta of the transistor then the curve drawn will be identical to the curve drawn in E-B mode, if the resistor selected is larger than the Beta of the transistor the curve drawn falls outward, if the resistor selected is smaller than the Beta of the transistor the curve drawn pulls inward. However this is never exact as the test circuit has no compensation for the E-B diode characteristics (a second approximation effect that changes between transistor types) and the curve sometimes begins falling outward then pulls inward.

A transistor on this tester should NEVER give any loops on any setting and the transistors on these cards are the first time I have encountered this! It means, for some reason, the transistor is stopping conduction far differently than it starts conduction. My suspicion is a thermal effect as I have seen many of the loops change size/shape the longer I leave the transistor on the tester.

I believe you took all those photos on one transistor.

--

R. Tim Coslet
(for e-mail address, go to Team Bois)


March 1 update from Robert Garner
Ron, Tim,

They're real: I've confirmed Tim's loopy/hysteresis I-V transistor curves on a Tek 7CT1N curve tracer plugin in my 7834 scope.

The 1st four traces are for NPN 083, bad sample #1, where horizontal collector voltage is about 2V/div, vertical collector current is 0.2 mA/div, and base step voltage amplitude is 10mV/step.
First screen pic is six base steps,
2nd one is single base voltage,
3rd one is eight,
4th is four base voltages (with these last two at 1mA/div collector current and 50mV and 100mV per steps, respectively).
Next two screen pics are 083, bad sample #2.
083-2,v=2V_div,i=1mA_divFour100mV
083-2,v=2V_div,i=1mA_divOne
And last screen pic is a good, "new old stock" NPN 2N1302, but at lower 20mV per base step.
Shows this new transistor has much better (~5x) beta than the loopy ones. (But I do see tiny loops in the higher base voltage traces too.)
Traces were rock solid and didn't move or change over time.

Any explanations?

(Mysterious ferromagnetic effect instigated by iron diffusion from wire leads into junction? ;-)

- Robert

Rick Dill's comments on "Loopy Transistors" - added July 2009
Robert Garner says Rick was later an IBM Fellow
The 1401 transistors were germanium, although at the end of the SMS days, silicon transistors were found that could be used as substitutes in most cases or at least replacement boards were made with silicon transistors that were voltage and signal level compatible.

The mode of loopy behavior in the silicon mesa transistors is similar to germanium. Mesa transistors had the collector diffused into the silicon over the entire wafer. The emitter was produced by a second diffusion or an alloy process (micro-epitaxy) and the emitter and base connections were covered with wax (or later photoresist) and were protected from an etch which went through the collector junction leaving the emitter and base on a tiny mesa of silicon. These junctions had no oxide protection except for the extremely thin native oxide and were sensitive to surface contamination as were the germanium emitter and collector junctions. The cans that transistors were put in or the plastic encapsulation of low cost transistors were to provide a hermetic seal and protect the sensitive collector junction. Contamination inside the can or any leaks resulted in leaky transistors.

The experimental tools we had were primitive compared to those even a few years later when we came first to really understand silicon junction passivation by oxides and through that to have some affirmation of what was deduced from primitive experiments for unprotected silicon and germanium junctions. There were some very early lessons from the solid logic technology (SLT) planar transistors used for the IBM 360. The theory of that design was that the transistors were protected by a low temperature powdered glass layer put onto the surface and then melted to give a hermetic seal to the junctions. This in theory would stabilize the transistors, but the theory didn't work because sodium atoms in the SiO2 layer lying under the frit glass layer were mobile ... unless the transistors had that locked up in a phosphosilicate glass layer from the emitter on NPN transistors. PNP transistors didn't have problems with surface inversion and were stable without the psg layer. That really didn't come out in technical publications until the advent of field effect transistors where the role of sodium in the SiO2 layer was a major issue in controlling both leakage and threshold voltage. IBM used PSG, while Intel and others essentially eliminated sodium by lots of washing before any thermal cycle which could lock fingerprints or other sodium contamination oxides.


an abstract with images

From the abstract, the article seems to be the first salvo in the common wisdom that "Cu is evil around Si"?:

(a) In the presence of bare copper in an oxygen free ambient, power aging degrades the emitter parameters and gain. Only partial recovery can be achieved by etching into the bulk silicon or by heating the device at 300°C (bulk failure). (b) In gold plated and/or oxygen backfilled cans, soft, loopy reverse junction characteristics develop under both temperature and power agings, first on the collector and later on the emitter. Both junctions. recover completely upon opening the can and drying the transistor surface (surface failure). Surface failure is caused by water adsorption over the surface of the silicon wafer. Experimental evidence, including aging experiments in atomic hydrogen, is presented to demonstrate that the bulk failure is caused by copper contamination in the bulk silicon. Copper is transferred from the can to the wafer via a volatile hydride. It diffuses into the silicon and becomes electrically active during power aging. Qualitative explanations are offered for both failure modes. Surface failure is due to surface states introduced by the adsorbed water and/or ionic conduction. In order to explain bulk failure, the solubility and precipitation of copper is examined over the transistor profile and the effect of field on the migration of copper in silicon is taken into account.

Some of their loopy curves:


return to
main page