Return to Geek-fun,-Hardware


by Carl Claunch
October 20, 2013

The 1401 is constructed with IBM's Standard Modular System, which is a packaging approach based on printed circuit cards and assemblies of those cards. IBM developed several different technology families which shared the SMS packaging, with two of those comprising the majority of the 1401 system - Complemented Transistor Diode Logic (CTDL) and current mode alloy junction transistor circuits. CTDL is slower and less expensive, used the most within the system, but current mode is employed to drive signals over long cables and for higher speed requirements. One other family, Complemented Transistor Resistor Logic (CTRL), is the slowest but lowest cost type of SMS logic; the 1401 does not use any CTRL as far as I know. The final SMS family is current mode diffused junction transistor circuits, the fastest and most expensive, also not used within the 1401 to my understanding. All the SMS families were built from discrete transistors and other components like resistors and diodes.

Digital logic is built with defined voltage levels that represent the binary state of a signal, designed so that variations in voltages caused by circuit loads, manufacturing tolerances for the components and noise are eliminated at each gate. The way this works hinges on the defined minimum and maximum voltages at the output of a gate being different than the minimum and maximum that a gate will accept as valid inputs. In addition, the bands of voltages that define a 1 and a 0 are seperate, leaving a gap that is commonly referred to as margin. Specifying a range or band of voltages that are considered equivalent digital values creates a safety margin to cover many deviations from ideal signal levels.

To see how this works, when a gate's output drives inputs of multiple gates, the output voltage is dragged down below the level when it is driving just one input. The gates are designed so the those differing levels at gate inputs are still valid 1 or 0 values, thanks to the range of voltages that define a binary value. The output of a gate is the same whether the input was a low but legitimate 1 or a full voltage 1, thus the variations are eliminated by each gate and brought back to the full standard levels.

The SMS system has a number of voltage levels defined to represent logical 1 and 0, depending on the logic family. The current mode families have two standards, N and P, which are based on the voltage that drives the two polarities of transistor, NPN or PNP. N type signals are appropriate to hook directly to an NPN transistor, while P signals are hooked directly to a PNP transistor. SMS has two reference voltage levels, around which the logic families will swing their voltages to represent 1 or 0 values. 0V is the reference for NPN transistors and N signal types, -6V is the reference for PNP transistors and P signal types.

Current mode circuits operate based on the current flowing into the transistor, since they are fundamentally a current amplifier or switch not a voltage sensitive device. N signals set 1 as +0.8V and 0 as -0.8V, although an input can be as small as +0.4V and still is validly a 1 (or as high as -0.4V and still be a valid 0). The output of current mode gates will be its full + or - 0.8V in spite of the inputs perhaps being degraded to a lower but valid voltage. The margin is the 0.4V difference from lowest to full voltage for each binary value.

IBM created two other logic families that operate more like a voltage sensitive device, but as a consequence are much slower because of the way the transistor has to operate (saturated mode). These are built to use a much, much wider swing in voltages between logical 1 and 0 states, permitting much more degradation or noise to occur without affecting correct operation. CTRL defines its signal voltages around the same 0V and -6V reference voltages as the current mode families, but with a bigger value for 1 and 0. The equivalent of the N signals of current mode, those referenced to 0V, are the R signals of CTRL and the T signals of CTDL. Cheapest and slowest, but with the most tolerance for degradation, CTRL defines an R signal 1 as +12V and a 0 to be -12V while CTDL defines its T signal 1 as +6V and its 0 as -6V, but all with a reference voltage of 0. CTRL and CTDL also use a 0V and a -6V voltage reference, same as with current modes, thus they too have pairs of signal standards R-S and T-U just as current mode has N-P.

In terms of widely recognized logic families,
- CTDL would be termed Diode-Transistor Logic (DTL -,
- and CTRL is an example of Resistor-Transistor Logic (RTL -
The SMS current mode families are closest to Emitter-Coupled Logic (ECL- which was invented by H Yourke of IBM although called current steering or current mode rather than the more modern name ECL.

IBM's naming of the signal levels likely stems from the physical correlation of N and P to the transistor types, but afterwards the naming comes from assigning sequential letters, R and S for the CTRL family and then T and U for the CTDL family. Sharp eyed readers will notice that Q is in the alphabet between P and R, but was not used for the signal names. IBM over the years exhibits a prediliction to skip certain letters of the alphabet when labeling connections and signals in their systems, in some cases due to the high chance of misreading one letter as a physically similar other letter (I is frequently skipped) and in this case they chose to skip over Q as a signal definition. Once could also assume that the letter R was chosen because the family was CTRL for resistor, but if that were the case one might expect CTDL signals to be D and E (D for diode) and they are not.

In CTDL, there are two sets of voltage levels, named T and U. As an example of the wide margins that exist in this family, a T signal output of a circuit will be a maximum of +6V when it represents a 1 and close to -6V when it represents a 0, but the signal could be smaller by the time it reaches the input of some other circuit or gate. Any input voltage of +1.4V and higher is accepted as a 1, yet the circuit delivers close to +6V as a 1 value output. An input voltage of -0.7V or lower is considered a valid 0 value, whereas the output will swing close to -6V to represent a 0. Weak transistors, loads from driving multiple gate inputs and other factors may cause the signal coming from the output of a gate to be less than +6V but as long as it doesn't fall below 1.4V, it is just as valid to represent a 1 state as a +6V input. Whether 6V, 4V or 1.5V, it is considered the same binary 1 condition as an input to some gate and the circuit must produce the same output for all of those input voltages. Each gate or circuit boosts the signals back much closer to the target of +6V or -6V, thus eliminating the variations that occur within each stage.

In the same way, CTDL defines U type signals where a logical 1 is 0V and a logical 0 will be -12V. The input voltage can be as low as -5.3V and still represent a 1, and a 0 is represented by any voltage from -7.4V down to -12. We should generally think only of the nominal or target voltages, those closest to what each gate produces as outputs - T signals as +6V or -6V, while U signals are 0V or -12V for their 1 and 0 states. Both of these types are a swing of + or - 6V from the reference voltage (-6V for U swings +6V to a net of 0 and swings -6V from the reference to reach -12V, while T swings +6V from 0 and -6V from the 0 reference.

Logic gates that implement functions such as OR use diodes, one way 'valves', as the heart of the logical operation, but each diode lowers the voltages of a signal. If either input to an OR is a 1 value, it is a positive voltage and will pass through a diode, whereas a 0 value for the input is a negative voltage that is blocked (it is a reverse voltage to the diode). Diodes also drop the voltage going through them by a value that is a characteristic of the particular diode. The voltage drop in signals from one set of diodes are passed to another set that further drop the voltage, and then to another, and another. These cumulative reductions must be eliminated otherwise a series of gates would progressively reduce the voltage of a 1 or 0 level until it was effectively zero, below the defined valid voltage such as +1.4V and unusable to denote a binary state. Redriving the voltages back to their target value, e.g. to +6V or -6V for T type signals, after each set of diode logic functions, allows gates to be strung in long chains yet still deliver useful voltages even to the last stage. The transistor is the 'amplifier' component that produces output voltages based on the logical input value, generating a target value regardless of the actual input voltage. Thus, CTDL is a diode based logic family using transistors to redrive the voltages of the signal coming from each gate.

One reason that the logic families have two signal standards, such as U and T, are because the circuits typically produce an output of the opposite type from the inputs - this uses the least number of components and keeps costs down. Thus, an OR gate may take T inputs and produce a U type output. Those U type signals from the first type of OR gate might be wired to a different OR circuit that accepts U signals as input and produces T signals as output. IBM calls the shift from one standard to another a 'translation'; most CTDL circuits are doing translation in addition to their main function. These circuits are also complemented in the sense that the gates are generally NOR and NAND - they use diodes to OR together signals, so that if any signal is positive (1) then the output is true but it is complemented to output as 0. If all inputs are 0, then and only then will the circuit output be 1 because the OR function is 0 before complementing. Said another way, the gate takes the result of an OR and then complements it (adding a NOT function).

Signals that will be sent long distances are converted to the P and N levels used by current mode circuits. N signals, use a maximum +3V for 1 and of -3V for 0, but are rarely anywhere near the higher levels. Inputs accept 0.4V up to 3V as a valid 1 input and accept -0.4V or lower as a valid 0. P signals could swing between -3V for a 1 and -9V for a 0, just to add to the confusion of different voltage levels found in a 1401. For example, in many circuits the actual highest output voltage might be 1.1V to -1.1V for N signals, triggering when the input swings past the thresholds of +0.4V and -0.4V from the opposite polarity.